40GBASE-LR4 40G Ethernet Links; InfiniBand DDR and QDR applications
40G Telecom connections
Description
The 40 QSFP+ LR4 2KM is a 4x10G hot-pluggable optical transceiver module. It is designed for up to 2KM optical communication applications over multimode fiber using 4 wavelength of CWDM via LC connectors. The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in ITU-T G694.2.
It is compliant with QSFP+ MSA, IEEE 802.3bm 40GBASE-LR4 standard.
It is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. With these features, this easy to install, hot swappable transceiver is suitable to be used in various applications, such as high-performance computing networks, enterprise core and distribution layer applications, data centers.
3. Electrical Characteristics (TOP = 0 to 70 °C, VCC = 3.13 to 3.47 Volts)
Parameter
Symbol
Min.
Typical
Max.
Unit
Note
Supply Voltage
Vcc
3.1
3.47
V
Supply Current
Icc
1000
mA
Transmit turn-on-time
2000
ms
1
Transmitter
Single Ended Output
Voltage Tolerance
Vin T
-0.3
4
V
Differential data input swing
Vin.pp
120
1200
mVpp
2
Differential input threshold
50
mV
AC common mode input voltage
tolerance (RMS)
15
mV
Differential input return loss
Per IEEE P802.3ba,Section 86A.4.1.1
dB
3
J2 Jitter Tolerance
Jt2
0.17
UI
J9 Jitter Tolerance
Jt9
0.29
UI
Data Dependent Pulse Width
Shrinkage
DDPWS
0.07
UI
Eye mask colordinates
{X1, X2 ,Y1, Y2}
0.11 , 0.31
95 , 350
UI
mV
4
Receiver
Single Ended Output Voltage Tolerance
-0.3
4
V
Differential data output swing
Vout,pp
0
800
mVpp
5,6
AC common mode output
voltage (RMS)
7.5
mV
Termination mismatch at 1 MHx
5
%
Differential output return loss
Per IEEE P802.3ba,Section 86A.4.2.1
dB
Common mode output
return loss
Per IEEE P802.3ba,Section 86A.4.2.1
ps
J2 Jitter output
Jo2
0.42
UI
J9 Jitter output
Jo9
0.65
UI
Eye mask colordinates #1
{X1, X2 ,Y1, Y2}
0.29, 0.50
150 , 425
UI
mV
4
Power Supply Ripple Tolerance
PSR
50
mVpp
Note:
1. From power-on and end of any fault conditions.
2. After internal AC coupling. Self-biasing 100Ω differential input.
3. 10 MHz to 11.1 GHz range
4.Hit ratio = 5 x 10E-5.
5.AC coupled with 100Ω differential output impedance.
6. Settable in 4 discrete steps via the I2C interface.
4. Optical Parameters(TOP = 0 to 70 °C, VCC = 3.14 to 3.46 Volts)
Parameter
Symbol
Min.
Typical
Max.
Unit
Ref.
Transmitter
Wavelength Assignment
L0
1264.5
1271
1277.5
nm
L1
1284.5
1291
1297.5
nm
L2
1304.5
1311
1317.5
nm
L3
1324.5
1331
1337.5
nm
Side-mode Suppression Ratio
SMSR
30
–
–
dB
Total Average Launch Power
PT
–
–
4.3
dBm
Average Launch Power, each Lane
-7
–
2.3
dBm
Difference in Launch Power between any two Lanes (OMA)
–
–
4
dB
Optical Modulation Amplitude,
each Lane
OMA
-4
2.5
dBm
Launch Power in OMA minus Transmitter and Dispersion Penalty (TDP), each Lane
Receive Electrical 3 dB upper Cut off Frequency, each Lane
12.3
GHz
RSSI Accuracy
-2
2
dB
Receiver Reflectance
Rrx
-26
dB
Receiver Power (OMA), each Lane
–
–
3.5
dBm
Receive Electrical 3 dB upper Cutoff Frequency, each Lane
12.3
GHz
LOS De-Assert
LOSD
-15
dBm
LOS Assert
LOSA
-25
dBm
LOS Hysteresis
LOSH
0.5
dB
Note: Measured with a PRBS 231-1 test pattern, @10.325Gb/s, BER<10-12.
5. Diagnostic Monitoring Interface
Digital diagnostics monitoring function is available on all QSFP+ SR4. A 2-wire serial interface provides user to contact with module. The structure of the memory is shown in flowing. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries, such as serial ID information and threshold settings, are available with the Page Select function. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL has been asserted, the host can read out the flag field to determine the affected channel and type of flag.
Byte Address
Description
Type
0
ldentifier(1 Byte)
Read Only
1-2
Status (2 Bytes)
Read Only
3-21
lnterrupt Flags (31 Bytes)
Read Only
22-33
Module Monitors (12 Bytes)
Read Only
34-81
Channel Monitors (48 Bytes)
Read Only
82-85
Reserved (4 Bytes)
Read Only
56-97
Control (12 Bytes)
Read Only
98-99
Reserved (2 Bytes)
Read Only
100-106
Module and Channel Masks (7 Bytes)
Read Only
107-118
Reserved (12 Bytes)
Read Only
119-122
Reserved (4 Bytes)
Read Only
123-126
Reserved (4 Bytes)
Read Only
127
Page Select Byte
Read Only
128-175
Module Thresholds (48 Bytes)
Read Only
176-223
Reserved(48 Bytes)
Read Only
224-225
Reserved(2 Bytes)
Read Only
226-239
Reserved(14 Bytes)
Read Only
240-240
Channel Controls (2 Bytes)
Read Only
242-253
Reserved(12 Bytes)
Read Only
254-255
Reserved (2 Bytes)
Read Only
6.Transceiver Block Diagram
7. Pin Assignment
8. Transceiver Block Diagram
Pin
Logic
Symbol
Max Unit Conditions
Ref.
1
GND
Ground
1
2
CML-I
Tx2n
Transmitter Inverted Data Input
3
CML-I
Tx2p
Transmitter Non-Inverted Data output
4
GND
Ground
1
5
CML-I
Tx4n
Transmitter Inverted Data Output
6
CML-I
Tx4p
Transmitter Non-Inverted Data Output
7
GND
Ground
1
8
LVTTL-I
ModSelL
Module Select
9
LVTTL-I
ResetL
Module Reset
10
VccRx
+3.3V Power Supply Receiver
2
11
LVCMOS-I/O
SCL
2-Wire Serial Interface Clock
12
LVCMOS-I/O
SDA
2-Wire Serial Interface Data
13
GND
Ground
1
14
CML-O
Rx3p
Receiver Inverted Data Output
15
CML-O
Rx3n
Receiver Non-Inverted Data Output
16
GND
Ground
1
17
CML-O
Rx1p
Receiver Inverted Data Output
18
CML-O
Rx1n
Receiver Non-Inverted Data Output
19
GND
Ground
1
20
GND
Ground
1
21
CML-O
Rx2n
Receiver Inverted Data Output
22
CML-O
Rx2p
Receiver Non-Inverted Data Output
23
GND
Ground
1
24
CML-O
Rx4n
Receiver Inverted Data Output
25
CML-O
Rx4p
Receiver Non-Inverted Data Output
26
GND
Ground
1
27
LVTTL-O
ModPrsL
Module Present
28
LVTTL-O
IntL
Interrupt
29
VccTx
+3.3V Power Supply Transmitter
2
30
Vcc1
+3.3V Power Supply
2
31
LVTTL-I
LPMode
Low Power Mode
32
GND
Ground
1
33
CML-I
Tx3p
Transmitter Inverted Data Output
34
CML-I
Tx3n
Transmitter Non-Inverted Data Output
35
GND
Ground
1
36
CML-I
Tx1p
Transmitter Inverted Data Output
37
CML-I
Tx1n
Transmitter Non-Inverted Data Output
38
GND
Ground
1
Note:
1.GND is the symbol for single and supply(power) common for QSFP modules, All are common within the QSFP module and all module voltages are referenced to this potential otherwise noted. Connect these directly to the host board signal common ground plane. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.
2.VccRx, Vcc1 and VccTx are the receiver and transmitter power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown below. VccRx, Vcc1 and VccTx may be internally connected within the QSFP transceiver module in any combination. The connector pins are each rated for maximum current of 500mA.
9.Recommended Circuit
10. Diagram Mechnical Drawing
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