The 40 QSFP+ LR4 2KM is a 4x10G hot-pluggable optical transceiver module. It is designed for up to 2KM optical communication applications over multimode fiber using 4 wavelength of CWDM via LC connectors. The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in ITU-T G694.2.
It is compliant with QSFP+ MSA, IEEE 802.3bm 40GBASE-LR4 standard.
It is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. With these features, this easy to install, hot swappable transceiver is suitable to be used in various applications, such as high-performance computing networks, enterprise core and distribution layer applications, data centers.
Receive Electrical 3 dB upper Cut off Frequency, each Lane
12.3
GHz
RSSI Accuracy
-2
2
dB
Receiver Reflectance
Rrx
-26
dB
Receiver Power (OMA), each Lane
–
–
3.5
dBm
Receive Electrical 3 dB upper Cutoff Frequency, each Lane
12.3
GHz
LOS De-Assert
LOSD
-25
dBm
LOS Assert
LOSA
-35
dBm
LOS Hysteresis
LOSH
0.5
dB
Note: 12dB Reflection
5. Diagnostic Monitoring Interface
Digital diagnostics monitoring function is available on all QSFP+ SR4. A 2-wire serial interface provides user to contact with module. The structure of the memory is shown in flowing. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries, such as serial ID information and threshold settings, are available with the Page Select function. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL has been asserted, the host can read out the flag field to determine the affected channel and type of flag.
Byte Address
Description
Type
0
ldentifier(1 Byte)
Read Only
1-2
Status (2 Bytes)
Read Only
3-21
lnterrupt Flags (31 Bytes)
Read Only
22-33
Module Monitors (12 Bytes)
Read Only
34-81
Channel Monitors (48 Bytes)
Read Only
82-85
Reserved (4 Bytes)
Read Only
56-97
Control (12 Bytes)
Read Only
98-99
Reserved (2 Bytes)
Read Only
100-106
Module and Channel Masks (7 Bytes)
Read Only
107-118
Reserved (12 Bytes)
Read Only
119-122
Reserved (4 Bytes)
Read Only
123-126
Reserved (4 Bytes)
Read Only
127
Page Select Byte
Read Only
128-175
Module Thresholds (48 Bytes)
Read Only
176-223
Reserved(48 Bytes)
Read Only
224-225
Reserved(2 Bytes)
Read Only
226-239
Reserved(14 Bytes)
Read Only
240-240
Channel Controls (2 Bytes)
Read Only
242-253
Reserved(12 Bytes)
Read Only
254-256
Reserved (2 Bytes)
Read Only
6. EEPROM Serial ID Memory Contents (A0h)
Data
Address
Length
(Byte)
Name of
Length
Description and Contents
6.1 Base ID Fields
128
1
Identifier
Identifier Type of serial Module(D=QSFP+)
129
1
Ext. Identifier
Extended Identifier of Serial Module(90=2.5W)
130
1
Connector
Code of connector type(7=LC)
131-138
8
Specification compliance
Code for electronic compatibility or optical compatibility(40GBASE-LR4)
139
1
Encoding
Code for serial encoding algorithm(5=64B66B)
140
1
BR, Nominal
Nominal bit rate, units of 100 MBits/s(6C=108)
141
1
Extended rateselect Compliance
Tags for extended rate select compliance
142
1
Length(SMF)
Link length supported for SMF fiber in km (28=40KM)
143
1
Length(OM3 50um)
Link length supported for EBW 50/125um fiber(OM3),
units of 2m
144
1
Length(OM2 50um)
Link length supported for 50/125um fiber(OM2),
units of 1m
145
1
Length(OM1 62.5um)
Link length supported for 62.5/125um fiber (OM1),
units of 1m
146
1
Length(Copper)
Link length of copper or active cable, unites of
1m Link length supported for 50/125um fiber (OM4),
units of 2m when Byte 147 declares 850nm VCSEL
as defined in Table 37
147
1
Device tech
Device technology
148-163
16
Vendor name
QSFP+ vendor name: TIBTRONIX (ASCII)
6.2 Base ID Fields
164
1
Extended Module
Extended Module codes for InfiniBand
165-167
3
Vendor OUI
QSFP+ vendor IEEE company ID(000840)
168-183
16
Vendor PN
Part number: hQPL40D (ASCII)
184-185
2
Vendor rev
Revision level for part number provided by vendor
(ASCII) (X1)
186-187
2
Wave length or Copper cable Attenuation
Nominal laser wavelength (wavelength=value/20 in nm)
or copper cable attenuation in dB at 2.5GHz (Adrs 186)
and 5.0GHz (Adrs 187) (65A4=1301)
188-189
2
Wavelength tolerance
Guaranteed range of laser wavelength(+/- value)
from nominal wavelength.
(wavelength Tol.=value/200 in nm) (1C84=36.5)
Indicates which types of diagnostic monitoring are implemented (if any) in the Module. Bit 1, 0 Reserved (8=Average Power)
221
1
Enhanced Options
Indicates which optional enhanced features
are implemented in the Module.
222
1
Reserved
223
1
CC_EXT
Check code for the Extended ID Fields (addresses 192-222)
6.4 Vendor Specific ID Fields
224-255
32
Vendor Specific EEPROM
7. Timing for Soft Control and Status Functions
Parameter
Symbol
Max
Unit
Conditions
Initialization Time
t_init
2000
ms
Time from power on1, hot plug or rising edge of Reset until the module is fully functional2
Reset Init Assert Time
t_reset_
init
2
μs
A Reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin.
Serial Bus Hardware
Ready Time
t_serial
2000
ms
Time from power on1 until module responds to data transmission over the 2-wire serial bus
Monitor Data Ready Time
t_data
2000
ms
Time from power on1 to data not ready, bit 0 of Byte 2, deasserted and IntL asserted
Reset Assert Time
t_reset
2000
ms
Time from rising edge on the ResetL pin until the module is fully functional2
LPMode Assert Time
ton_
LPMode
100
μs
Time from assertion of LPMode (Vin:LPMode =Vih) until module power consumption enters lower Power Level
IntL Assert Time
ton_IntL
200
ms
Time from occurrence of condition triggering IntL until Vout:IntL = Vol
IntL Deassert Time
toff_IntL
500
μs
toff_IntL 500 μs Time from clear on read3 operation of associated flag until Vout:IntL = Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits.
Rx LOS Assert Time
ton_los
100
ms
Time from Rx LOS state to Rx LOS bit set and IntL asserted
Flag Assert Time
ton_flag
200
ms
Time from occurrence of condition triggering flag to associated flag bit set and IntL asserted
Mask Assert Time
ton_mask
100
ms
Time from mask bit set4 until associated IntL assertion is inhibited
Mask De-assert Time
toff_mask
100
ms
Time from mask bit cleared4 until associated IntlL operation resumes
ModSelL Assert Time
ton_
ModSelL
100
μs
Time from assertion of ModSelL until module responds to data transmission over the 2-wire serial bus
ModSelL Deassert Time
toff_
ModSelL
100
μs
Time from deassertion of ModSelL until the module does not respond to data transmission over the 2-wire serial bus
Power_over-ride or
Power-set Assert Time
toff_
Pdown
100
ms
Time from P_Down bit set 4 until module power consumption enters lower Power Level
Power_over-ride or
Power-set De-assert Time
toff_
Pdown
300
ms
Time from P_Down bit cleared4 until the module is fully functional3
Note:
1. Power on is defined as the instant when supply voltages reach and remain at or
above the minimum specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 de-asserted.
3. Measured from falling clock edge after stop bit of read transaction.
4. Measured from falling clock edge after stop bit of write transaction.
8.Transceiver Block Diagram
9. Pin Assignment
10. Transceiver Block Diagram
Pin
Logic
Symbol
Max Unit Conditions
Ref.
1
GND
Ground
1
2
CML-I
Tx2n
Transmitter Inverted Data Input
3
CML-I
Tx2p
Transmitter Non-Inverted Data output
4
GND
Ground
1
5
CML-I
Tx4n
Transmitter Inverted Data Output
6
CML-I
Tx4p
Transmitter Non-Inverted Data Output
7
GND
Ground
1
8
LVTTL-I
ModSelL
Module Select
9
LVTTL-I
ResetL
Module Reset
10
VccRx
+3.3V Power Supply Receiver
2
11
LVCMOS-I/O
SCL
2-Wire Serial Interface Clock
12
LVCMOS-I/O
SDA
2-Wire Serial Interface Data
13
GND
Ground
1
14
CML-O
Rx3p
Receiver Inverted Data Output
15
CML-O
Rx3n
Receiver Non-Inverted Data Output
16
GND
Ground
1
17
CML-O
Rx1p
Receiver Inverted Data Output
18
CML-O
Rx1n
Receiver Non-Inverted Data Output
19
GND
Ground
1
20
GND
Ground
1
21
CML-O
Rx2n
Receiver Inverted Data Output
22
CML-O
Rx2p
Receiver Non-Inverted Data Output
23
GND
Ground
1
24
CML-O
Rx4n
Receiver Inverted Data Output
25
CML-O
Rx4p
Receiver Non-Inverted Data Output
26
GND
Ground
1
27
LVTTL-O
ModPrsL
Module Present
28
LVTTL-O
IntL
Interrupt
29
VccTx
+3.3V Power Supply Transmitter
2
30
Vcc1
+3.3V Power Supply
2
31
LVTTL-I
LPMode
Low Power Mode
32
GND
Ground
1
33
CML-I
Tx3p
Transmitter Inverted Data Output
34
CML-I
Tx3n
Transmitter Non-Inverted Data Output
35
GND
Ground
1
36
CML-I
Tx1p
Transmitter Inverted Data Output
37
CML-I
Tx1n
Transmitter Non-Inverted Data Output
38
GND
Ground
1
Note:
1.GND is the symbol for single and supply(power) common for QSFP modules, All are common within the QSFP module and all module voltages are referenced to this potential otherwise noted. Connect these directly to the host board signal common ground plane. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.
2.VccRx, Vcc1 and VccTx are the receiver and transmitter power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown below. VccRx, Vcc1 and VccTx may be internally connected within the QSFP transceiver module in any combination. The connector pins are each rated for maximum current of 500mA.
11. Recommended Circuit
12. Diagram Mechnical Drawing
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