Zion Code and Description
|Zion Code||Zion Description|
|7211030||100G QSFP28 LR4 CWDM 2KM LC SMF Fiber Optical Transceiver|
- Data Center and LAN
100G QSFP28 LR4 is designed to operate over single-mode fiber system using 4X25 CWDM channel in 1310 band and links up to 2km. The module converts 4 inputs channel of 25Gb/s electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for 100Gb/s optical transmission. Reversely, on the receiver side, the module optically de-multiplexes a 100Gb/s input into 4 CWDM channels signals, and converts them to 4 channel output electrical data.
The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm. It contains a duplex LC connector for the optical interface and a 38-pin connector for the electrical interface. Single-mode fiber (SMF) is applied in this module. This product converts the 4-channel 25Gb/s electrical input data into CWDM optical signals (light), by a 4-wavelength Distributed Feedback Laser (DFB) array. The 4 wavelengths are multiplexed into a single 100Gb/s data, propagating out of the transmitter module via the SMF. The receiver module accepts the 100Gb/s optical signals input, and de-multiplexes it into 4 CWDM 25Gb/s channels. Each wavelength light is collected by a discrete photo diode, and then outputted as electric data after amplified by a TIA.
The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP28 Multi-Source Agreement (MSA) and compliant to IEEE 802.3ba.
Main product parameters
|Form Factor||QSFP28||Max Data Rate||100 Gbps|
|Max Cable Distance||2KM||Connector type||LC|
|Fiber cable Type||SMF||Vendor Name||ZION COMMUNICATION|
|Transimitter Type||DFB CWDM||Receiver Type||PIN|
|Transmit Power||– 6.5 to +2.5 dBm||Max Receiver
|– 10.1 dBm|
|Overload Power||2.5 dBm||Extinction Ratio||3.5 dB|
|DDM||Supported||Operating Temp.||0°C to 70°C (32°F to 158°F)|
Zion Communication’s Hot 100G transceiver types
|Zion Code||Zion Description|
|7211010||100G QSFP28 SR4 850nm 100M MPO MMF Fiber Optic Transceiver|
|7211020||100G QSFP28 PSM4 1310nm 2KM MPO SMF Fiber Optic Transceiver|
|7211030||100G QSFP28 LR4 CWDM 2KM LC SMF Fiber Optic Transceiver|
|7211050||100G QSFP28 LR4 LAN WDM 10KM LC SMF Fiber Optic Transceiver|
|7211060||100G QSFP28 ER4 LAN WDM 30KM/40KM LC SMF Fiber Optic Transceiver|
|7211070||100G QSFP28 ZR4 LAN WDM 80KM LC SMF Fiber Optic Transceiver|
Detailed product specifications
1 Absolute Maximum Ratings
|Storage Temperature (℃）||TS||-40||85||°C|
|Power Supply Voltage||VCC||-0.3||4||V|
|Signal Input Voltage||Vin||Vcc-0.3||Vcc+0.3||V|
2 Recommended Operating Environment
|Case operating Temperature||TOP||0||70||°C||Without
|Power Supply Voltage||VCC||3.13||3.3||3.47||V|
|Power Supply Current||ICC||900||mA|
|Data Rate||BR||25.78125||Gbps||Each Channel|
|Transmission Distance with||TD||0||2||km|
3 Electrical Characteristics (TOP = 0 to 70 °C, VCC = 3.14 to 3.46 Volts)
|Input differential impedance||Rin||100||Ω||1|
|Differential data input swing||Vin.pp||180||1000||mV|
|Transmit Disable Voltage||VD||Vcc–1.3||Vcc||V|
|Transmit Enable Voltage||VEN||Vee||Vee+ 0.8||V||2|
|Differential data output swing||Vout.pp||300||850||mV||3|
|Data output rise time||tr||28||ps||4|
|Data output fall time||tf||28||ps||4|
|LOS Fault||VLOS fault||Vcc–1.3||VccHOST||V||5|
|LOS Normal||VLOS norm||Vee||Vee+0.8||V||5|
|Power Supply Rejection||PSR||100||mVpp||6|
1) Connected directly to TX data input pins. AC coupled thereafter.
2) Or open circuit.
3) Into 100 ohms differential termination.
4) 20 – 80 %.
5) Loss Of Signal is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
Receiver sensitivity is compliant with power supply sinusoidal modulation of 20 Hz to 1.5 MHz up to specified value applied through
the recommended power supply filtering network.
4 Optical Characteristics
|Total Output. Power||POUT||8.5||dBm|
|Average Launch Power Per lane||-6.5||2.5||dBm|
|Spectral Width (-20dB)||σ||1||nm|
|Optical Extinction Ratio||ER||3.5||dB|
|Average launch Power off per lane||Poff||-30||dBm|
and Dispersion Penalty per lane
|Output Eye Mask definition
|Rx Sensitivity per lane||RSENS||-10||dBm||1|
|Input Saturation Power (Overload)||Psat||2.5||dBm|
1) Measured with a PRBS 231-1 test pattern, @25.78Gb/s, BER<10-12 .
6 Transceiver Block Diagram
|1||GND||Transmitter Ground (Common with Receiver Ground)||1|
|2||Tx2n||Transmitter Inverted Data Input|
|3||Tx2p||Transmitter Non-Inverted Data output|
|4||GND||Transmitter Ground (Common with Receiver Ground)||1|
|5||Tx4n||Transmitter Inverted Data Input|
|6||Tx4p||Transmitter Non-Inverted Data output|
|7||GND||Transmitter Ground (Common with Receiver Ground)||1|
|10||VccRx||3.3V Power Supply Receiver||2|
|11||SCL||2-Wire serial Interface Clock|
|12||SDA||2-Wire serial Interface Data|
|13||GND||Transmitter Ground (Common with Receiver Ground)|
|14||Rx3p||Receiver Non-Inverted Data Output|
|15||Rx3n||Receiver Inverted Data Output|
|16||GND||Transmitter Ground (Common with Receiver Ground)||1|
|17||Rx1p||Receiver Non-Inverted Data Output|
|18||Rx1n||Receiver Inverted Data Output|
|19||GND||Transmitter Ground (Common with Receiver Ground)||1|
|20||GND||Transmitter Ground (Common with Receiver Ground)||1|
|21||Rx2n||Receiver Inverted Data Output|
|22||Rx2p||Receiver Non-Inverted Data Output|
|23||GND||Transmitter Ground (Common with Receiver Ground)||1|
|24||Rx4n||Receiver Inverted Data Output||1|
|25||Rx4p||Receiver Non-Inverted Data Output|
|26||GND||Transmitter Ground (Common with Receiver Ground)||1|
|29||VccTx||3.3V power supply transmitter||2|
|30||Vcc1||3.3V power supply||2|
|31||LPMode||Low Power Mode|
|32||GND||Transmitter Ground (Common with Receiver Ground)||1|
|33||Tx3p||Transmitter Non-Inverted Data Input|
|34||Tx3n||Transmitter Inverted Data Output|
|35||GND||Transmitter Ground (Common with Receiver Ground)||1|
|36||Tx1p||Transmitter Non-Inverted Data Input|
|37||Tx1n||Transmitter Inverted Data Output|
|1||GND||Transmitter Ground (Common with Receiver Ground)||1|
1) GND is the symbol for signal and supply (power) common for QSFP28 modules. All are common within the QSFP28 module
and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal
common ground plane.
2) VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended
host board power supply filtering is shown below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP28
transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.
7 Digital Diagnostic Functions
100G QSFP28 LR4 2KM support the 2-wire serial communication protocol as defined in the QSFP28 MSA.
Which allows real-time access to the following operating parameters:
Laser bias current
Transmitted optical power
Received optical power
Transceiver supply voltage
It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected.
The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 -QSFP28 Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.
For more detailed information including memory map definitions, please see the QSFP28 MSA Specification.
8 Host – Transceiver Interface Block Diagram
9 Outline Dimensions